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RT9199
Cost-Effective, 2A Peak Sink/Source Bus Termination Regulator
General Description
The RT9199 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the devices requirements. The regulator is capable of actively sinking or sourcing up to 2A peak while regulating an output voltage to within 20mV. The output termination voltage can be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the REFEN pin voltage. The RT9199 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The RT9199 are available in both SOP-8 and SOP-8 (Exposed Pad) surface mount packages.
Features
Ideal for DDR-II VTT Applications Sink and Source 2A Peak Current Integrated Power MOSFETs Generate Termination Voltage for DDR Memory Interfaces High Accuracy Output Voltage at Full-Load Output Adjustment by Two External Resistors Low External Component Count Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output Current Limiting Protection On-Chip Thermal Protection RoHS Compliant and 100% Lead (Pb)-Free
Applications
Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR/II Memory Systems
Ordering Information
RT9199 Package Type S : SOP-8 SP : SOP-8 (Exposed Pad-Option 2) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
Note : Richtek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100%matte tin (Sn) plating.
Pin Configurations
(TOP VIEW)
VIN GND REFEN VOUT 2 3 4 8 7 6 5 VCNTL VCNTL VCNTL VCNTL
SOP-8
VIN GND REFEN VOUT 2 3 8 GND 6 9 4 5 7 NC NC VCNTL NC
SOP-8 (Exposed Pad)
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Typical Application Circuit
VCNTL = 5V VIN = 1.8V R1 VIN VCNTL CIN CCNTL RTT
2N7002 EN R2 CSS
RT9199 REFEN VOUT GND COUT RDUMMY
R1 = R2 = 100k, RTT = 50 / 33 / 25 COUT(MIN) = 10F (Ceramic) + 1000F under the worst case testing condition RDUMMY = 1k as for VOUT discharge when VIN is not presented but VCNTL is presented CSS = 1F, CIN = 470F (Low ESR), CCNTL = 47F
Test Circuit
VIN = 1.8V VCNTL = 5V
VIN 1.25V
VCNTL VOUT COUT IL
RT9199 REFEN VOUT GND
V
Figure 1. Output Voltage Tolerance, VLOAD
VCNTL = 5V VIN = 1.8V
A
VIN VCNTL VOUT COUT 0.9V 0V
0.9V 0.15V
RT9199 VOUT REFEN GND RL
V
RL and COUT Time deleay
Figure 2. Current in Shutdown Mode, ISTBY
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VIN = 1.8V VCNTL = 5V
VIN 0.9V
VCNTL VOUT
RT9199 REFEN VOUT GND
A
IL
COUT
V
Figure 3. Current Limit for High Side, ILIM
Power Supply with Current Limit VIN = 1.8V VIN 0.9V
VCNTL = 5V
VCNTL
A
IL VOUT COUT
RT9199 VOUT REFEN GND
V
Figure 4. Current Limit for Low Side, ILIM
VCNTL = 5V VIN = 1.8V VIN 0.9V VREFEN 0.15V VCNTL VOUT COUT
RT9199 VOUT REFEN GND RL
V
0.9V VOUT 0V
VOUT would be low if VREFEN < 0.15V VOUT would be high if VREFEN > 0.6V RL and COUT Time deleay
Figure 5. REFEN Pin Shutdown Threshold, VIH & VIL
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Functional Pin Description
VIN Input voltage which supplies current to the output pin. Connect this pin to a well-decoupled supply voltage. To prevent the input rail from dropping during large load transient, a large, low ESR capacitor is recommended to use. The capacitor should be placed as close as possible to the VIN pin. GND (Exposed Pad) Common Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. VCNTL VCNTL supplies the internal control circuitry and provides the drive voltage. The driving capability of output current is proportioned to the VCNTL. Connect this pin to 5V bias supply to handle large output current with at least 1F capacitor from this pin to GND. An important note is that VIN should be kept lower or equal to VCNTL. REFEN Reference voltage input and active low shutdown control pin. Two resistors dividing down the VIN voltage on the pin to create the regulated output voltage. Pulling the pin to ground turns off the device by an open-drain, such as 2N7002, signal N-MOSFET. VOUT Regulator output. VOUT is regulated to REFEN voltage that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output rail. To maintain adequate large signal transient response, typical value of 1000F Al electrolytic capacitor with 10F ceramic capacitors are recommended to reduce the effects of current transients on VOUT.
Function Block Diagram
VCNTL VIN
Current Limit Thermal Protection
REFEN
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+ -
EA
VOUT
GND
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Absolute Maximum Ratings
(Note 1) Input Voltage, VIN ------------------------------------------------------------------------------------------------------ 6V Control Voltage, VCNTL ----------------------------------------------------------------------------------------------- 6V Power Dissipation, PD @ TA = 25C SOP-8 ------------------------------------------------------------------------------------------------------------------- 0.909W SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------------------- 1.176W Package Thermal Resistance (Note 4) SOP-8, JA -------------------------------------------------------------------------------------------------------------- 110 C/W SOP-8, JC -------------------------------------------------------------------------------------------------------------- 60 C/W SOP-8 (Exposed Pad), JA ------------------------------------------------------------------------------------------ 86 C/W SOP-8 (Exposed Pad), JC ----------------------------------------------------------------------------------------- 15 C/W Junction Temperature ------------------------------------------------------------------------------------------------- 125C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260C Storage Temperature Range ---------------------------------------------------------------------------------------- -65C to 150C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
Input Voltage, VIN ------------------------------------------------------------------------------------------------------ 1.6V to 5.5V Control Voltage, VCNTL ----------------------------------------------------------------------------------------------- 5V 5% Junction Temperature Range ---------------------------------------------------------------------------------------- -40C to 125C
Electrical Characteristics
(VIN = 1.8V, VCNTL = 5V, VREFEN = 0.9V, COUT = 10F (Ceramic), TA = 25C, unless otherwise specified)
Parameter Input VCNTL Operation Current Standby Current (Note 7) Output (DDR II) Output Offset Voltage (Note 5) Load Regulation (Note 6) Protection Current limit
Symbol ICNTL ISTBY IOUT = 0A
Test Conditions
Min ---
Typ 1 2
Max Units 2.5 90 mA A
VREFEN < 0.2V (Shutdown), RLOAD = 180 IOUT = 0A IOUT = +1.8A IOUT = -1.8A
VOS VLOAD
-20 -20
---
+20 +20
mV mV
ILIMIT VCNTL = 5V VCNTL = 5V Enable Shutdown TSD VIH VIL
2.0 125 -0.6 --
-170 35 ---
3.5 ---0.15
A C C
Thermal Shutdown Temperature TSD Thermal Shutdown Hysteresis REFEN Shutdown Shutdown Threshold
V
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Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. JA is measured in the natural convection at TA = 25C on a high effective thermal conductivity test board (4 Layers, 2S2P) of JEDEC 51-7 thermal measurement standard. The case point of JC is on the exposed pad for SOP-8 (Exposed Pad) package. Note 5. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. Note 6. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A peak. Note 7. Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on REFEN pin (VIL < 0.15V). It is measured with VIN = VCNTL = 5V.
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Typical Operating Characteristics
Output Voltage vs. Temperature
0.92 0.915
VCNTL Pin Current vs. Temperature
0.6
VIN = 1.8V, VCNTL = 5V
VIN = 1.8V, VCNTL = 5V
Output Voltage (V)
0.91 0.905 0.9 0.895 0.89 0.885 0.88 -50 -25 0 25 50 75 100 125
Vcntl Pin Current (mA)
0.5
0.4
0.3
0.2
0.1 -50 -25 0 25 50 75 100 125
Temperature (C)
Temperature (C)
Source Current Limit vs. Temperature
3.5 3
Sink Current Limit vs. Temperature
3.5 3
VIN = 1.8V, VCNTL = 5V
VIN = 1.8V, VCNTL = 5V
Source Current Limit (A)
2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125
Source Current Limit (A)
2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125
Temperature (C)
Temperature (C)
VIN Current vs. Temperature
3 2.5
Shutdown Threshold vs. Temperature
0.6 0.55
VIN = 1.8V, VCNTL = 5V
RT9199 SP, VCNTL = 5V
Shutdown Threshold (V)
VIN Current (mA)
0.5 0.45 0.4 0.35 0.3 0.25 0.2
2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125
Turn On
Turn Off
-50
-25
0
25
50
75
100
125
Temperature (C)
Temperature (C)
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Output Short-Circuit Protection
Sink VIN = 1.8V, VCNTL = 5V
Output Short-Circuit Protection
Sink VIN = 2.5V, VCNTL = 5V
12
Output Short Circuit (A)
12
Output Short Circuit (A)
10 8 6 4 2 0
10 8 6 4 2 0
Time (1ms/Div)
Time (1ms/Div)
Output Short-Circuit Protection
Source VIN = 1.8V, VCNTL = 5V
Output Short-Circuit Protection
Source VIN = 2.5V, VCNTL = 5V
12
Output Short Circuit (A) Output Short Circuit (A)
12 10 8 6 4 2 0
10 8 6 4 2 0
Time (1ms/Div)
Time (1ms/Div)
0.9VTT @ 1.8A Transient Response
Output Voltage Transient (mV)
1.25VTT @ 1.8A Transient Response
Output Voltage Transient (mV) Output Current (A)
VIN = 2.5V, VCNTL = 5V, VOUT = 1.25V
VIN = 1.8V, VCNTL = 5V, VOUT = 0.9V
50 Swing Frequency : 10kHz 0 -50 2
50 Swing Frequency : 10kHz 0 -50 2 1 0 -1 -2
Output Current (A)
1 0 -1 -2 Time (25s/Div)
Time (25s/Div)
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Application Information
Consideration while designing the resistance of voltage divider Refer to the "Typical Application Circuit".Make sure the current sinking capability of pull-down NMOS is enough for the chosen voltage divider to pull-down the voltage at REFEN pin below 0.15V to shutdown the device. In addition, the capacitor CSS and voltage divider form the low-pass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. How to reduce power dissipation on Notebook PC or the dual channel DDR SDRAM application? In notebook application, using RichTek's Patent
"Distributed
0.48 0.46 0.44 0.42
could be obtained by the product of RDS(ON) and output current. For thermal consideration, please refer to the relative sections.
VREFEN VCNTL VIN
R1
RT9199 REFEN VOUT R2 GND
Figure 6
RDS(ON) vs. Temperature
VCNTL = 5V, VREFEN = 1V
Bus Terminator Topology" with choosing RichTek's product is encouraged.
Distributed Bus Terminating Topology
Terminator Resistor
R DS(ON) ()
R0 R1
BUS(0) BUS(1)
0.4 0.38 0.36 0.34 0.32 0.3 0.28 -50 -25 0 25 50 75 100 125
RT9199
VOUT
R2 R3 R4
BUS(2) BUS(3) BUS(4) BUS(5) BUS(6)
REFEN R5 R6 VOUT R7 R8 R9
Temperature (C)
RT9199
BUS(7) BUS(8) BUS(9)
Figure 7 Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the RT9199. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between RT9199 and the preceding power converter. Thermal Consideration RT9199 regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. For continued operation, do not exceed absolute maximum operation junction temperature 125C. The power dissipation definition in device is: PD = (VIN - VOUT) x IOUT + VIN x IQ
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R(2N) R(2N+1)
BUS(2N) BUS(2N+1)
General Regulator The RT9199 could also serves as a general linear regulator. The RT9199 accepts an external reference voltage at REFEN pin and provides output voltage regulated to this reference voltage as shown in Figure 6, where VOUT = VREFEN x R2/(R1+R2) As other linear regulator, dropout voltage and thermal issue should be specially considered. Figure 7 shows the RDS(ON) over temperature of RT9199. The minimum dropout voltage
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The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: PD(MAX) = ( TJ(MAX) - TA ) / JA Where T J(MAX) is the maximum operation junction temperature 125C, TA is the ambient temperature and the JA is the junction to ambient thermal resistance. The junction to ambient thermal resistance for SOP-8 package (Exposed Pad) is 86C/W, on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25C can be calculated by following formula: PD(MAX) = (125C - 25C) / 86C/W = 1.163W Figure 8 shows the package sectional drawing of SOP-8 (Exposed Pad). Every package has several thermal dissipation paths. As show in Figure 9, the thermal resistance equivalent circuit of SOP-8 (Exposed Pad). The path 2 is the main path due to these materials thermal conductivity. We define the exposed pad is the case point of the path 2.
Ambient Molding Compound Gold Line
The thermal resistance JA of SOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it' s useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of SOP-8 package. Figure 10 show the relation between thermal resistance JA and copper area on a standard JEDEC 51-7 (4 layers, 2S2P) thermal test board at TA = 25C. We have to consider the copper couldn' t stretch infinitely and avoid the tin overflow. We use the "Dog-Bone" copper patterns on the top layer as Figure 11.
100
Thermal Resistance JA (C/W)
90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50
2
60
70
80
Lead Frame
Copper Area (mm )
Die Pad PCB Case (Exposed Pad)
Figure 10. Relation Between Thermal Resistance JA and Copper Area
Figure 8. SOP-8 (Exposed Pad) Package Sectional Drawing
Exposed Pad
RGOLD-LINE path 1 RDIE
RLEAD FRAME
RPCB
W2.28mm
Junction
RDIE-ATTACH RDIE-PAD path 2
RPCB
Case (Exposed Pad)
Ambient
RMOLDING-COMPOUND path 3
Figure 11. Dog-Bone Layout
Figure 9. Thermal Resistance Equivalent Circuit
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As shown in Figure 12, the amount of copper area to which the SOP-8 (Exposed Pad) is mounted affects thermal performance. When mounted to the standard SOP-8 (Exposed Pad) pad of 2 oz. copper (Figure 12.a), JA is 86C/W. Adding copper area of pad under the SOP-8 (Exposed Pad) (Figure 12.b) reduces the JA to 73C/W. Even further, increasing the copper area of pad to 70mm2 (Figure 12.d) reduces the JA to 65C/W.
(a) Copper Area = 10mm2, JA = 86C/W
(b) Copper Area = 30mm2, JA = 73C/W
(c) Copper Area = 50mm2, JA = 68C/W
(d) Copper Area = 70mm2, JA = 65C/W Figure 12. Thermal Resistance vs. Copper Area Layout Thermal Design
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Outline Information
A
H M
J
B
F
C I D
Dimensions In Millimeters Symbol Min A B C D F H I J M 4.801 3.810 1.346 0.330 1.194 0.170 0.050 5.791 0.400 Max 5.004 3.988 1.753 0.508 1.346 0.254 0.254 6.200 1.270
Dimensions In Inches Min 0.189 0.150 0.053 0.013 0.047 0.007 0.002 0.228 0.016 Max 0.197 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050
8-Lead SOP Plastic Package
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A H M EXPOSED THERMAL PAD (Bottom of Package) Y J X B
F
C I D
Dimensions In Millimeters Symbol A B C D F H I J M Option 1 X Y X Y Min 4.801 3.810 1.346 0.330 1.194 0.170 0.000 5.791 0.406 2.000 2.000 2.100 3.000 Max 5.004 4.000 1.753 0.510 1.346 0.254 0.152 6.200 1.270 2.300 2.300 2.500 3.500
Dimensions In Inches Min 0.189 0.150 0.053 0.013 0.047 0.007 0.000 0.228 0.016 0.079 0.079 0.083 0.118 Max 0.197 0.157 0.069 0.020 0.053 0.010 0.006 0.244 0.050 0.091 0.091 0.098 0.138
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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